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serial input, voltage output 12-/14-bit digital-to-analog converters ad5530/ad5531 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features pin-compatible 12-, 14-bit digital-to-analog converters serial input, voltage output maximum output voltage range of 10 v data readback 3-wire serial interface clear function to a user-defined voltage power-down function serial data output for daisy-chaining 16-lead tssop applications industrial automation automatic test equipment process control general-purpose instrumentation functional block diagram 0 0938-001 ldac rben refagnd sdin power-down control logic dac register refin 12-/14-bit dac r r gnd sclk sync sdo r r v out dutgnd v dd v ss shift register ad5530/ad5531 clr pd figure 1. general description the ad5530/ad5531 are single 12- and 14-bit (respectively) serial input, voltage output digital-to-analog converters (dac). they utilize a versatile 3-wire interface that is compatible with spi?, qspi?, microwire?, and dsp interface standards. data is presented to the part in a 16-bit serial word format. serial data is available on the sdo pin for daisy-chaining purposes. data readback allows the user to read the contents of the dac register via the sdo pin. the dac output is buffered by a gain of two amplifier and referenced to the potential at dutgnd. ldac can be used to update the output of the dac asynchronously. a power-down pin ( pd ) allows the dac to be put into a low power state, and a clr pin allows the output to be cleared to a user-defined voltage, the potential at dutgnd. the ad5530/ad5531 are available in 16-lead tssop.
ad5530/ad5531 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac performance characteristics ................................................ 5 standalone timing characteristics............................................ 5 daisy-chaining and readback timing characteristics.......... 6 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 12 theory of operation ...................................................................... 13 dac architecture....................................................................... 13 serial interface ............................................................................ 13 pd function................................................................................ 13 readback function .................................................................... 13 clr function.............................................................................. 13 output voltage............................................................................ 14 bipolar configuration................................................................ 14 microprocessor interfacing........................................................... 15 ad5530/ad5531 to adsp-21xx.............................................. 15 ad5530/ad5531 to 8051 interface ......................................... 15 ad5530/ad5531 to mc68hc11 interface ............................ 15 applications information .............................................................. 17 optocoupler interface................................................................ 17 serial interface to multiple ad5530s or ad5531s ................ 17 daisy-chaining interface with multiple ad5530s or ad5531s ...................................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 1/07rev. a to rev. b updated format..................................................................universal changes to figure 28...................................................................... 17 3/06rev. 0 to rev. a change to table 3 ............................................................................. 5 change to figure 4 ........................................................................... 8 change to output voltage section............................................... 14 change to ordering guide............................................................ 18 5/02revision 0: initial version
ad5530/ad5531 rev. b | page 3 of 20 specifications v dd = 15 v 10%; v ss = ?15 v 10%; gnd = 0 v; r l = 5 k and c l = 220 pf to gnd. all specifications t min to t max , unless otherwise noted. table 1. parameter 1 ad5530 ad5531 unit test conditions/comments accuracy resolution 12 14 bits relative accuracy 1 2 lsb max differential nonlinearity 1 1 lsb max guaranteed monotonic over temperature zero-scale error 2 8 lsb max typically within 1 lsb full-scale error 2 8 lsb max typically within 1 lsb gain error 1 4 lsb typ gain temperature coefficient 2 0.5 0.5 ppm fsr/c typ 10 10 ppm fsr/c max reference inputs 2 reference input range 0 to 5 0 to 5 v min to v max max output range 10 v dc input resistance 100 100 m typ input current 1 1 a max per input, typically 20 na dutgnd input 2 dc input impedance 60 60 k typ max input current 0.3 0.3 ma typ input range ?4 to +4 ?4 to +4 v min to v max max output range 10 v o/p characteristics 2 output voltage swing 10 10 v max short-circuit current 15 15 ma max resistive load 5 5 k min to 0 v capacitive load 1200 1200 pf max to 0 v dc output impedance 0.5 0.5 max digital i/o v inh , input high voltage 2.4 2.4 v min v inl , input low voltage 0.8 0.8 v max i inh , input current 10 10 a max total for all pins c in , input capacitance 2 10 10 pf max 3 pf typical sdo v ol , output low voltage 0.4 0.4 v max i sink = 1 ma power requirements v dd /v ss +15/?15 +15/?15 v nom 10% for specified performance power supply sensitivity full scale/v dd 110 110 db typ full scale/v ss 100 100 db typ i dd 2 2 ma max outputs unloaded i ss 2 2 ma max outputs unloaded i dd in power-down 150 150 a max typically 50 a 1 temperature range for b version: ?40c to +85c. 2 guaranteed by design, not subject to production test.
ad5530/ad5531 rev. b | page 4 of 20 v dd = 12 v 10%; v ss = ?12 v 10%; gnd = 0 v; r l = 5 k and c l = 220 pf to gnd; t a = t min to t max , unless otherwise noted. table 2. parameter 1 ad5530 ad5531 unit test conditions/comments accuracy resolution 12 14 bits relative accuracy 1 2 lsb max differential nonlinearity 1 1 lsb max guaranteed monotonic over temperature zero-scale error 2 8 lsb max typically within 1 lsb full-scale error 2 8 lsb max typically within 1 lsb gain error 1 4 lsb typ gain temperature coefficient 2 0.5 0.5 ppm fsr/c typ 10 10 ppm fsr/c max reference inputs 2 reference input range 0 to 4.096 0 to 4.096 v min to v max max output range 8.192 v dc input resistance 100 100 m typ input current 1 1 a max per input, typically 20 na dutgnd input 2 dc input impedance 60 60 k typ max input current 0.3 0.3 ma typ input range ?3 to +3 ?3 to +3 v min to v max max output range 8.192 v o/p characteristics 2 output voltage swing 8.192 8.192 v max short-circuit current 15 15 ma max resistive load 5 5 k min to 0 v capacitive load 1200 1200 pf max to 0 v dc output impedance 0.5 0.5 max digital i/o v inh , input high voltage 2.4 2.4 v min v inl , input low voltage 0.8 0.8 v max i inh , input current 10 10 a max total for all pins c in , input capacitance 2 10 10 pf max 3 pf typical sdo v ol , output low voltage 0.4 0.4 v max i sink = 1 ma power requirements v dd /v ss +12/?12 +12/?12 v nom 10% for specified performance power supply sensitivity full scale/v dd 110 110 db typ full scale/v ss 100 100 db typ i dd 2 2 ma max outputs unloaded i ss 2 2 ma max outputs unloaded i dd in power-down 150 150 a max typically 50 a 1 temperature range for b version: ?40c to +85c. 2 guaranteed by design, not subject to production test.
ad5530/ad5531 rev. b | page 5 of 20 ac performance characteristics v dd = 10.8 v to 16.5 v, v ss = ?10.8 v to ?16.5 v; gnd = 0 v; r l = 5 k and c l = 220 pf to gnd. all specifications t min to t max , unless otherwise noted. table 3. parameter b version unit test conditions/comments dynamic performance output voltage settling time 20 s typ full-scale change to ? lsb. dac latch contents alternately loaded with all 0s and all 1s. slew rate 1.3 v/s typ digital-to-analog glitch impulse 120 nv-s typ dac latch alternately loaded with 0x0fff and 0x1000. not dependent on load conditions. digital feedthrough 0.5 nv-s typ effect of input bus activity on dac output under test. output noise spectral density @ 1 khz 100 nv/hz typ all 1s loaded to dac. standalone timing characteristics v dd = 10.8 v to 16.5 v, v ss = ?10.8 v to ?16.5 v; gnd = 0 v; r l = 5 k and c l = 220 pf to gnd. all specifications t min to t max , unless otherwise noted. table 4. parameter limit at t min , t max unit description 1 , 2 f max 7 mhz max sclk frequency t 1 140 ns min sclk cycle time t 2 60 ns min sclk low time t 3 60 ns min sclk high time t 4 50 ns min sync to sclk falling edge setup time t 5 40 ns min sclk falling edge to sync rising edge t 6 50 ns min min sync high time t 7 40 ns min data setup time t 8 15 ns min data hold time t 9 5 ns min sync high to ldac low t 10 50 ns min ldac pulse width t 11 5 ns min ldac high to sync low t 12 50 ns min clr pulse width 1 guaranteed by design, not subject to production test. 2 sample tested during initial release and after any redesign or process change that can affect this parameter. all input signal s are measured with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. sclk sync sdin msb db15 db14 db11 db0 lsb t 1 t 3 t 2 t 5 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 ldac 1 clr 1 ldac can be tied permanently low, if required. 0 0938-002 figure 2. timing diagram for standalone mode
ad5530/ad5531 rev. b | page 6 of 20 daisy-chaining and readback timing characteristics v dd = 10.8 v to 16.5 v, v ss = ?10.8 v to ?16.5 v; gnd = 0 v; r l = 5 k and c l = 220 pf to gnd. all specifications t min to t max , unless otherwise noted. table 5. parameter limit at t min , t max unit description 1 , 2 , 3 f max 2 mhz max sclk frequency t 1 500 ns min sclk cycle time t 2 200 ns min sclk low time t 3 200 ns min sclk high time t 4 50 ns min sync to sclk falling edge setup time t 5 40 ns min sclk falling edge to sync rising edge t 6 50 ns min min sync high time t 7 40 ns min data setup time t 8 15 ns min data hold time t 12 50 ns min clr pulse width t 13 130 ns min sclk falling edge to sdo valid t 14 50 ns max sclk falling edge to sdo invalid t 15 50 ns min rben to sclk falling edge setup time t 16 50 ns min rben hold time t 17 100 ns min rben falling edge to sdo valid 1 guaranteed by design, not subject to production test. 2 sample tested during initial release and after any redesign or process change that can affect this parameter. all input signal s are measured with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 sdo; r pullup = 5 k, c l = 15 pf 00938-003 sclk sync sdin sdo (daisy- chaining) rben sdo (readback) msb db15 db14 db11 db0 db15 db11 db0 lsb msb lsb msb lsb rb0 rb13 00 t 1 t 3 t 2 t 5 t 4 t 6 t 7 t 8 t 13 t 14 t 15 t 16 t 13 t 14 t 17 figure 3. timing diagram for daisy-chaining and readback mode
ad5530/ad5531 rev. b | page 7 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ?0.3 v to +17 v v ss to gnd +0.3 v to ?17 v digital inputs to gnd ?0.3 v to v dd + 0.3 v sdo to gnd ?0.3 v to +6.5 v refin to refagnd ?0.3 v to +17 v refin to gnd v ss ? 0.3 v to v dd + 0.3 v esd caution refagnd to gnd v ss ? 0.3 v to v dd + 0.3 v dutgnd to gnd v ss ? 0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature (t j max ) 150c package power dissipation (t j max C t a )/ ja thermal impedance ja tssop (ru-16) 150.4c/w lead temperature (soldering 10 sec) 300c ir reflow, peak temperature (<20 sec) 235c
ad5530/ad5531 rev. b | page 8 of 20 pin configuration and function descriptions refagnd 1 refin 2 ldac 3 sdin 4 sync 5 rben 6 sclk 7 sdo 8 v dd 16 v out 15 dutgnd 14 v ss 13 nc 12 gnd 11 pd 10 clr 9 ad5530/ ad5531 top view (not to scale) nc = no connect 0 0938-004 figure 4. pin configuration table 7. pin function descriptions pin no. nemonic description 1 refagnd for bipolar 10 v output range, this pin should be tied to 0 v. 2 refin this is the voltage reference input for the dac. connect to external 5 v reference for specified bipolar 10 v output . 3 ldac load dac logic input (active low). when taken low, the contents of the shift register are transferred to the dac register. ldac can be tied permanently low, enabling the o utputs to be updated on the rising edge of sync . 4 sdin serial data input. this device accepts 16-bit words. da ta is clocked into the input register on the falling edge of sc lk. 5 sync active low control input. data is clocked into th e shift register on the falling edges of sclk. 6 rben active low readback enable function. this function al lows the contents of the dac register to be read. data from the dac register is shifted out on the sdo pin on each rising edge of sclk. 7 sclk clock input. data is clocked into th e input register on the falling edge of sclk. 8 sdo serial data out. this pin is used to clock out the serial data previously writte n to the input shift register or can be used in conjunction with rben to read back the data from the dac re gister. this is an open drain output; it should be pulled high with an external pull-up resistor. in standalone mode, sdo should be tied to gnd or left high impedance. 9 clr level sensitive, active low input. a falling edge of clr resets v out to dutgnd. the contents of the registers are untouched. 10 pd this allows the dac to be put into a power-down state. 11 gnd ground reference. 12 nc do not connect anything to this pin. 13 v ss negative analog supply voltage. ?12 v 10% or ?15 v 10%, for specified performance. 14 dutgnd v out is referenced to the voltage applied to this pin. 15 v out dac output. 16 v dd positive analog supply voltage. 12 v 10% or 15 v 10%, for specified performance.
ad5530/ad5531 rev. b | page 9 of 20 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 lsb code 00938-005 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v t a = 25c 1.00 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 0 2000 4000 6000 8000 10000 12000 14000 16000 lsb code 00938-008 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v t a = 25c figure 5. ad5530 typical inl plot figure 8. ad5531 typical dnl plot 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 lsb code 00938-006 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v t a = 25c 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?40 80 60 40 20 0 ?20 error (lsb) temperature (c) 00938-009 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v figure 6. ad5530 typical dnl plot figure 9. ad5531 typical inl error vs. temperature 1.0 ?1.0 ?0.8 ?0.6 ?0.2 ?0.4 0 0.2 0.4 0.6 0.8 ?40 80 60 40 20 0 ?20 error (lsb) temperature (c) 00938-010 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 lsb code 00938-007 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v t a = 25c figure 10. ad5531 typical dnl error vs. temperature figure 7. ad5531 typical inl plot
ad5530/ad5531 rev. b | page 10 of 20 3 2 1 ?3 ?2 ?1 0 2.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 error (lsb) refin voltage (v) 00938-011 v dd = +15v v ss = ?15v refin = 0v t a = 25c negative inl positive inl 0.03 0.02 0.01 0 10 17 16 15 14 13 12 11 +85c +25c ?40c i dd (ma) supply voltage (v) 00938-014 figure 11. ad5531 typical inl error vs. reference voltage figure 14. i dd in power-down vs. supply 0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 ?40 ?20 0 20 40 60 80 error (lsb) temperature (c) 00938-012 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v 12 8 4 0 ?4 ?8 ?12 0 5 10 15 20 25 v out (v) time (s) 00938-015 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v t a = 25c figure 12. typical full-scale and offset error vs. temperature figure 15. settling time 1.50 1.45 1.40 1.35 1.30 1.25 1.20 10 17 16 15 14 13 12 11 +85c +25c ?40c current (ma) v dd /v ss (v) 00938-013 0 ?0.16 ?0.14 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 v out (v) time (750ns/div) 00938-016 v dd = +15v v ss = ?15v refin = +5v refagnd = 0v t a = 25c figure 13. i dd vs. v dd /v ss figure 16. typical digital-to-analog glitch impulse
ad5530/ad5531 rev. b | page 11 of 20 0 0938-017 v out 2v/div 2v/div pd v dd = +15v v ss = ?15v refin = +5v refagnd = 0v t a = 25c figure 17. typical power-down time
ad5530/ad5531 rev. b | page 12 of 20 terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is a measure of the output error when all 0s are loaded to the dac latch. full-scale error this is the error in dac output voltage when all 1s are loaded into the dac latch. ideally the output voltage, with all 1s loaded into the dac latch, should be 2 v ref ? 1 lsb. gain error gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. it is the deviation in slope of the dac transfer characteristic from ideal. output voltage settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.
ad5530/ad5531 rev. b | page 13 of 20 theory of operation 00938-020 sdo ldac 12-/14-bit dac dac register sync register 16-bit shift register sync sdin refin 14 14 14 output dac architecture the ad5530/ad5531 are pin-compatible 12- and 14-bit dacs. the ad5530 consists of a straight 12-bit r-2r voltage mode dac, and the ad5531 consists of a 14-bit r-2r section. using a 5 v reference connected to the refin pin and refagnd tied to 0 v, a bipolar 10 v voltage output results. the dac coding is straight binary. serial interface serial data on the sdin input is loaded to the input register under the control of sclk, sync ldac , and . a write operation transfers a 16-bit word to the ad5530/ad5531. figure 2 and figure 3 show the timing diagrams. figure 18 and figure 20. simplified serial interface figure 19 show the contents of the input shift register. twelve or 14 bits of the serial word are data bits; the rest are dont cares. data written to the part via sdin is available on the sdo pin 16 clocks later if the readback function is not used. sdo data is clocked out on the falling edge of the serial clock with some delay. db15 (msb) xx d9 d10d11 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x db0 (lsb) data bits 00938-018 pd function figure 18. ad5530 input shift register contents pd the pin allows the user to place the device into power-down mode. while in this mode, power consumption is at a minimum; the device draws only 50 a of current. the xx d11 d12 d13 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db15 (msb) db0 (lsb) 00938-019 data bits pd function does not affect the contents of the dac register. figure 19. ad5531 input shift register contents readback function sync the serial word is framed by the signal, . after a high-to- low transition on the ad5530/ad5531 allows the data contained in the dac register to be read back if required. the pins involved are the sync , data is latched into the input shift register on the falling edges of sclk. there are two ways the dac register and output can be updated. the ldac signal is examined on the falling edge of sync ; depending on its status, either a synchronous or asynchronous update is selected. if ldac is low, then the dac register and output are updated on the low-to-high transition of sync . alternatively, if ldac is high upon sampling, the dac register is not loaded with the new data on a rising edge of sync . the contents of the dac register and the output voltage are updated by bringing ldac low any time after the 16-bit data transfer is complete. ldac can be tied permanently low if required. a simplified diagram of the input loading circuitry is illustrated in figure 20 . rben rben and sdo (serial data out). when is taken low, on the next falling edge of sclk, the contents of the dac register are transferred to the shift register. rben can be used to frame the readback data by leaving it low for 16 clock cycles, or it can be asserted high after the required hold time. the shift register contains the dac register data and this is shifted out on the sdo line on each falling edge of sclk with some delay. this ensures the data on the serial data output pin is valid for the falling edge of the receiving part. the two msbs of the 16-bit word are 0s. clr function the falling edge of clr causes v out to be reset to the same potential as dutgnd. the contents of the registers remain unchanged, so the user can reload the previous data with ldac after clr is asserted high. alternatively, if ldac is tied low, the output is loaded with the contents of the dac register auto- matically after clr is brought high.
ad5530/ad5531 rev. b | page 14 of 20 0 0938-021 c1 1f r1 10k? 9 2 6 +15 v v out v out dutgnd gnd signal gnd signal gnd 1 additional pins omitted for clarity. v out (?10v to +10v) refin refagnd ad5530/ ad5531 1 v ss ?15v 5 4 ad586 output voltage the dac transfer function is as follows: n d 2 v out = 2 [2 (( refin ? refagnd ) ) + 2 refagnd ? refin ] ? dutgnd where: d is the decimal data-word loaded to the dac register. n is the resolution of the dac. bipolar configuration figure 21 shows the ad5530/ad5531 in a bipolar circuit configuration. refin is driven by the ad586, 5 v reference, and the refagnd and dutgnd pins are tied to gnd. this results in a bipolar output voltage ranging from ?10 v to +10 v. resistor r1 is provided (if required) for gain adjust. figure 21. bipolar 10 v operation 00938-022 2 refin ?2 refin dac input code 000 001 (3)fff dac output voltage 0v figure 22 shows the transfer function of the dac when refagnd is tied to 0 v. figure 22. output voltage vs. dac input codes (hex)
ad5530/ad5531 rev. b | page 15 of 20 microprocessor interfacing microprocessor interfacing to the ad5530/ad5531 is via a serial bus that uses standard protocol compatible with micro- controllers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5530/ad5531 requires a 16-bit data-word with data valid on the falling edge of sclk. the 8051 provides the lsb of its sbuf register as the first bit in the data stream. the user has to ensure that the data in the sbuf register is arranged correctly because the dac expects msb first. ad5530/ ad5531 1 80c51/80l51 1 1 additional pins omitted for clarity. ldac p3.4 sync p3.3 sdin rxd sclk txd 00938-024 for all the interfaces, the dac output update can be done automatically when all the data is clocked in or asynchronously under the control of ldac . the contents of the dac register can be read using the readback function. figure 24. ad5530/ad5531 to 8051 interface rben is used to frame the readback data, which is clocked out on sdo. figure 23, figure 24, and figure 25 show these dacs interfacing with a simple 4-wire interface. the serial interface of the ad5530/ad5531 can be operated from a minimum of three wires. when data is to be transmitted to the dac, p3.3 is taken low. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result no glue logic is required between this dac and microcontroller interface. the 8051 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. as the dac expects a 16-bit word, p3.3 must be left low after the first 8 bits are transferred. after the second byte has been transferred, the p3.3 line is taken high. the dac can be updated using ad5530/ad5531 to adsp-21xx an interface between the ad5530/ad5531 and the adsp-21xx is shown in figure 23 . in the interface example shown, sport0 is used to transfer data to the dac. the sport control register should be configured as follows: internal clock operation, alternate framing mode; active low framing signal. ldac via p3.4 of the 8051. ad5530/ad5531 to mc68hc11 interface transmission is initiated by writing a word to the tx register after the sport has been enabled. as the data is clocked out of the dsp on the rising edge of sclk, no glue logic is required to interface the dsp to the dac. in the interface shown, the dac output is updated using the figure 25 shows an example of a serial interface between the ad5530/ad5531 and the mc68hc11 microcontroller. sck of the mc68hc11 drives the sclk of the dac, and the mosi output drives the serial data lines, sdin. sync is driven from one of the port lines, in this case pc7. ldac pin via the dsp. alternatively, the ldac input could be tied permanently low and then the update takes place automatically when tfs is taken high. ad5530/ ad5531 1 mc68hc11 1 1 additional pins omitted for clarity. ldac pc6 sync pc7 sdin mosi sclk sck 00938-025 ad5530/ ad5531 1 adsp-2101/ adsp-2103 1 1 additional pins omitted for clarity. ldac fo sync tfs sdin dt sclk sclk 00938-023 figure 25. ad5530/ad5531 to mc68hc11 interface the mc68hc11 is configured for master mode, mstr = 1, cpol = 0, and cpha = 1. when data is transferred to the part, pc7 is taken low and data is transmitted msb first. data appearing on the mosi output is valid on the falling edge of sck. eight falling clock edges occur in the transmit cycle, so to load the required 16-bit word, pc7 is not brought high until the second 8-bit word has been transferred to the dac input shift register. figure 23. ad5530/ad5531 to adsp-21xx interface ad5530/ad5531 to 8051 interface a serial interface between the ad5530/ad5531 and the 8051 is shown in figure 24 . txd of the 8051 drives sclk of the ad5530/ad5531, while rxd drives the serial data line, sdin. p3.3 and p3.4 are bit-programmable pins on the serial port and are used to drive sync and ldac , respectively.
ad5530/ad5531 rev. b | page 16 of 20 ldac is controlled by the pc6 port output. the dac can be updated after each 2-byte transfer by bringing ldac low. this example does not show other serial lines for the dac. if clr were used, it could be controlled by port output pc5. to read data back from the dac register, the sdo line can be connected to miso of the mc68hc11, with rben tied to another port output controlling and framing the readback data transfer.
ad5530/ad5531 rev. b | page 17 of 20 applications information serial interface to multiple ad5530s or ad5531s optocoupler interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. opto-isolators can provide voltage isolation in excess of 3 kv. the serial loading structure of the ad5530/ ad5531 makes it ideal for opto-isolated interfaces because the number of interface lines is kept to a minimum. sync figure 26 shows a 4-channel isolated interface to the ad5530/ad5531. to reduce the number of opto-isolators, if simultaneous updating is not required, then the ldac pin can be tied permanently low. 00938-026 controller control out to ldac sync out to sync serial clock out to sclk serial data out to sdin optocoupler v cc figure 26. opto-isolated interface figure 27 shows how the pin is used to address multiple ad5530/ad5531s. all devices receive the same serial clock and serial data, but only one device receives the sync signal at any one time. the dac addressed is determined by the decoder. there is some feedthrough from the digital input lines, the effects of which can be minimized by using a burst clock. 00938-027 ad5530/ad5531 1 v out sync sdin sclk ad5530/ad5531 1 v out sync sdin sclk ad5530/ad5531 1 v out sync sdin sclk ad5530/ad5531 1 v out sync sdin sclk sclk sdin v cc decoder 1 enable en coded address dgnd 1 additional pins omitted for clarity. figure 27. addressing multiple ad5530/ad5531s daisy-chaining interface with multiple ad5530s or ad5531s a number of these dac parts can be daisy-chained together using the sdo pin. figure 28 illustrates such a configuration. 0 0938-028 ad5530/ad5531 1 sdo sclk sdin sync sclk sdin s ync ad5530/ad5531 1 sdo sclk sdin sync ad5530/ad5531 1 sdo sclk sdin sync to other serial devices v dd r r r 1 additional pins omitted for clarity. figure 28. daisy-chaining multiple ad5530/ad5531s
ad5530/ad5531 rev. b | page 18 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 29. 16-lead thin shrink small outline package (tssop) (ru-16) dimensions shown in millimeters ordering guide model temperature range resolution inl (lsbs) dnl (lsbs) package description package option ad5530bru ?40c to +85c 12 1 1 16-lead tssop ru-16 ad5530bru-reel ?40c to +85c 12 1 1 16-lead tssop ru-16 ad5530bru-reel7 ?40c to +85c 12 1 1 16-lead tssop ru-16 ad5530bruz ?40c to +85c 12 1 1 16-lead tssop ru-16 1 ad5530bruz-reel ?40c to +85c 12 1 1 16-lead tssop ru-16 1 ad5530bruz-reel7 ?40c to +85c 12 1 1 16-lead tssop ru-16 1 ad5531bru ?40c to +85c 14 2 1 16-lead tssop ru-16 ad5531bru-reel ?40c to +85c 14 2 1 16-lead tssop ru-16 ad5531bru-reel7 ?40c to +85c 14 2 1 16-lead tssop ru-16 AD5531BRUZ ?40c to +85c 14 2 1 16-lead tssop ru-16 1 AD5531BRUZ-reel ?40c to +85c 14 2 1 16-lead tssop ru-16 1 AD5531BRUZ-reel7 ?40c to +85c 14 2 1 16-lead tssop ru-16 1 1 z = pb-free part.
ad5530/ad5531 rev. b | page 19 of 20 notes
ad5530/ad5531 rev. b | page 20 of 20 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c00938-0-1/07(b)

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